GAL16V8 PLD

In shop today we programmed up a Binary to Seven Segment Hex Display Decoder. Unlike the 74LS47 Seven Segment Decoder it can not display above 10. With the GAL16V8 we can programming in CUPL we can make our own custom designed gates. We also  have the option of changing pin outs that makes it so much more flexible than standard 74 and 40 series logic. This is a first step as a basic building block as we head into the more complex VHDL and FPGA design.

The GAL16V8 PLD (Programmable Logic Device), combines a high performance CMOS process with Electrically Erasable (E2 ) floating gate technology to provide the highest speed performance available in the PLD. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.

GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture.

Below are some pictures

Below is the CUPL code, once compiled we

can take the JDEC  and program the GAL

Here is the programmer we used, I bought this on amazon.

 The TL866CS

Here is the example circuit on the protoboard

Below is a video of the example circuit working

One problem we ran into was we could not download the software, the site was blocked by the school firewall, so I downloaded it via my cell phone on a 4G network. Once this is done you will have to rename the file extension to send it by email or the filter will think it's a virus. This ate up a lot of our time getting this to work.